Crate rhdl_ed25519_sim 

Simulation report, waveform, Verilog-normalization, and checksum utilities.

The run_simulations binary drives real top-level commands and message handshakes through the RHDL simulator and checks results against rhdl_ed25519_model. The export_verilog binary emits synthesizable RTL. This library keeps generated evidence deterministic and records the pinned Dalek/RHDL source commits beside every summary.

Structs

SimCase

One named simulation check in a machine-readable report.

SimReport

Complete simulation summary and source pins.

TraceEvent

Compact state transition recorded for VCD/SVG generation.

Functions

ensure_generated_dir

Create and return generated_dir.

generated_dir

Return the workspace-relative generated-report directory.

sha256_file

Compute a lowercase SHA-256 checksum for one file.

split_wide_binary_literals

Rewrite over-wide exact-width Verilog binary literals as concatenations.

write_checksum_manifest

Write deterministic SHA-256 rows for every regular file in dir.

write_compact_vcd

Write a small standards-compliant VCD from sparse trace events.

write_state_timeline_svg

Write an SVG timeline whose segments are labeled controller states.

write_waveform_svg

Write a compact digital-lane SVG used in generated simulation reports.