Module code_map 

Code map

The workspace is split by hardware responsibility rather than by mathematical chapter. This table is the quickest route from a failing test or waveform to the owning crate.

Public boundary and oracle

Crate	Responsibility	Start with
[rhdl_ed25519_api]	Dalek Signer, Verifier, MultipartSigner, and MultipartVerifier adapters over a hardware transport	Ed25519Hardware, HardwareSigningKey
[rhdl_ed25519_types]	command, message, pass-request, result, operation, flag, and error encodings	Ed25519Command, Ed25519Result
[rhdl_ed25519_model]	pinned-Dalek reference behavior and RFC/vector helpers	sign, verify_strict, canonical_vectors

Compatibility arithmetic

Crate	Responsibility	Important detail
rhdl_ed25519_sha512	streaming SHA-512, padding, circular schedule, K ROM	hashes actual bytes in RTL
rhdl_ed25519_hash_feeder	prefix insertion, message framing, 4 KiB replay cache	owns external-byte counters
rhdl_ed25519_field	field arithmetic modulo 2^255 - 19	ten alternating 26/25-bit limbs
rhdl_ed25519_scalar	scalar reduction/canonical checks modulo group order l	nine 29-bit limbs internally
rhdl_ed25519_point	extended Edwards formulas and Niels conversion	microcoded field-operation DAG
rhdl_ed25519_scalar_mul	radix-16 scalar recoding and constant-pattern table scan	builds eight point multiples on demand
rhdl_ed25519_point_codec	compression and decompression controller	coordinates inversion, square root, and canonical checks
rhdl_ed25519_point_codec_*	decompression sub-kernels and shared types	split to keep RHDL kernels tractable

[rhdl_ed25519_core] re-exports these arithmetic crates into the logical field, sha512, scalar, point, hash_feeder, and types namespaces. New code should generally depend on the owning crate for implementation and on the facade when assembling an engine.

Compatibility control plane

Crate	Responsibility
[rhdl_ed25519_controller_types]	top-level input/output and state/status types
rhdl_ed25519_transition	pure next-state function
rhdl_ed25519_commands	child-engine command construction
rhdl_ed25519_registers	retained cache/work/point register updates
rhdl_ed25519_result	result and error formation
[rhdl_ed25519_top]	child wiring, arbitration, and top-level synchronous design

When adding a state, update the state constant, transition, child command, register capture, result behavior, and tests together. Do not hide a state transition inside a register-update kernel.

Fast fixed-64 path

Crate	Current responsibility	Status
[rhdl_ed25519_fast_field]	radix-2^17, II=1 DSP field-multiply prototype and behavioral model	primitive RTL and tests
[rhdl_ed25519_fast_fixed_base]	generated Dalek fixed-base table assets, constant-pattern lookup, recoding/scheduler RTL	integration in progress
basepoint_table_gen	parse the pinned Dalek table and emit checked radix-17 ROM assets	deterministic generation tool

The fast backend is deliberately not wired into [rhdl_ed25519_top] yet. Contributors should preserve that separation until the fast top signs and validates complete messages.

Simulation, RTL, FPGA, and host code

Path	Responsibility
rhdl_ed25519_sim	cycle simulation, trace generation, checksums, Verilog export
bench/rhdl	Vitis RTL kernel shell and AXI data movement
bench/host	common XRT host benchmark and result collection
bench/amd	AMD Vitis Security comparison kernel
tools/vivado	out-of-context synthesis and implementation scripts
reports/generated	generated evidence; inspect provenance before citing

Generated Verilog and Vivado reports are evidence, not source. A source change invalidates a prior synthesis claim unless the report records and matches the new source checksum.