Module shells_and_benchmarks 

AXI kernel, benchmark engines, register maps, and traffic behavior.

AXI Shells and Benchmark Logic

The cryptographic core exposes simple ready/valid signals. Vitis needs AXI-Lite control and AXI memory masters, while a focused on-chip benchmark needs a deterministic request generator. The modules here provide those roles; they do not change Ed25519 arithmetic.

fast64_cached_sign_io_kernel

Source: bench/rhdl/rtl/fast64_cached_sign_io_kernel.sv.

This is the current deployment wrapper around fast64_cached_sign_core. It has one AXI4-Lite slave and four independent 512-bit AXI4 memory masters.

Parameters

Parameter	Default	Meaning
C_S_AXI_CONTROL_ADDR_WIDTH	7	AXI-Lite control address width
C_S_AXI_CONTROL_DATA_WIDTH	32	AXI-Lite data width; the register logic assumes 32 bits
C_M_AXI_GMEM0_ADDR_WIDTH	64	Message-master address width
C_M_AXI_GMEM0_DATA_WIDTH	512	Message-master data width; the datapath assumes one 64-byte message per beat
C_M_AXI_GMEM0_ID_WIDTH	1	Message-master AXI ID width
C_M_AXI_GMEM1_ADDR_WIDTH	64	Key/command-master address width
C_M_AXI_GMEM1_DATA_WIDTH	512	Key/command-master data width
C_M_AXI_GMEM1_ID_WIDTH	1	Key/command-master AXI ID width
C_M_AXI_GMEM2_ADDR_WIDTH	64	Signature-master address width
C_M_AXI_GMEM2_DATA_WIDTH	512	Signature-master data width; one signature occupies one beat
C_M_AXI_GMEM2_ID_WIDTH	1	Signature-master AXI ID width
C_M_AXI_GMEM3_ADDR_WIDTH	64	Summary-master address width
C_M_AXI_GMEM3_DATA_WIDTH	512	Summary-master data width; all counters occupy one beat
C_M_AXI_GMEM3_ID_WIDTH	1	Summary-master AXI ID width

The current RTL drives ARSIZE/AWSIZE=6, meaning 64-byte transfers. Changing a data-width parameter without changing the state machines and size constants is unsupported.

Clock, reset, and interrupt ports

Port	Direction	Meaning
ap_clk	input	Kernel and core clock
ap_rst_n	input	Active-low shell reset, inverted to active-high areset internally
interrupt	output	Global-enable AND enabled interrupt-status bits

AXI-Lite control ports

Channel	Ports	Behavior
Write address	s_axi_control_AWVALID, AWREADY, AWADDR	Address is retained independently until write data is also present
Write data	s_axi_control_WVALID, WREADY, WDATA, WSTRB	Byte strobes produce a 32-bit write mask
Write response	s_axi_control_BVALID, BREADY, BRESP	Returns AXI OKAY; protocol errors are not separately encoded here
Read address	s_axi_control_ARVALID, ARREADY, ARADDR	Accepts one outstanding register read
Read data	s_axi_control_RVALID, RREADY, RDATA, RRESP	Returns AXI OKAY; reading control clears the latched done bit

The table omits the repeated s_axi_control_ prefix after the first name but names every signal suffix present in the module.

AXI memory-master ports

For each m_axi_gmemN master, the complete port contract is:

AXI channel	Outputs from kernel	Inputs to kernel
Write address	AWVALID, AWADDR, AWID, AWLEN, AWSIZE, AWBURST, AWLOCK, AWCACHE, AWPROT, AWQOS, AWREGION	AWREADY
Write data	WVALID, WDATA, WSTRB, WLAST	WREADY
Write response	BREADY	BVALID, BRESP, BID
Read address	ARVALID, ARADDR, ARID, ARLEN, ARSIZE, ARBURST, ARLOCK, ARCACHE, ARPROT, ARQOS, ARREGION	ARREADY
Read data	RREADY	RVALID, RDATA, RLAST, RID, RRESP

The prefix identifies purpose:

Master	Active direction	Purpose
m_axi_gmem0	Read only	Read one 512-bit message at messages + tag*stride_lines*64
m_axi_gmem1	Read only	Read the 32-byte key seed in the low half of one command beat
m_axi_gmem2	Write only	Write one signature beat at signatures + tag*64
m_axi_gmem3	Write only	Write one summary beat at the configured summary pointer

Unused channel directions are tied inactive; response/read inputs on those directions are reduced into unused_inputs to suppress lint warnings.

All active transfers are single-beat incrementing bursts with LEN=0, SIZE=6, BURST=INCR, ID zero, cache value 0011, and no protection, QoS, or region override.

Operation constants

Constant	Value	Meaning
OP_SIGN_WARM	2	Sign batch fixed-64 messages using the cached key
OP_LOAD_CACHED_KEY	4	Clear the old key, read one seed beat, expand it, and retain the new key
OP_CLEAR_CACHED_KEY	5	Clear the key without reading memory
DUMMY_TAG	0xffff	Internal tag for an odd-batch padding request; never written as a signature

Control register map

Local parameter/address	Register
ADDR_AP_CTRL / 0x00	Start, done, idle, ready, and auto-restart bits
ADDR_GIE / 0x04	Global interrupt enable
ADDR_IER / 0x08	Interrupt enables
ADDR_ISR / 0x0c	Toggle-on-write interrupt status
ADDR_MESSAGES_LO, ADDR_MESSAGES_HI / 0x10, 0x14	64-bit message base address
ADDR_COMMANDS_LO, ADDR_COMMANDS_HI / 0x1c, 0x20	64-bit key/command base address
ADDR_RESULTS_LO, ADDR_RESULTS_HI / 0x28, 0x2c	64-bit signature base address
ADDR_COUNTERS_LO, ADDR_COUNTERS_HI / 0x34, 0x38	64-bit summary destination
ADDR_STRIDE_LO, ADDR_STRIDE_HI / 0x40, 0x44	Message stride measured in 64-byte lines
ADDR_MSG_LEN_LO, ADDR_MSG_LEN_HI / 0x4c, 0x50	Message length; warm sign requires exactly 64
ADDR_BATCH / 0x58	Number of real signatures requested, limited to 65,535 by 16-bit tags
ADDR_OPERATION / 0x60	One of the operation constants above

arg_* registers are software-visible. They are copied into run_* registers when start is accepted so software writes cannot alter an active command.

Run-state machine

State	Function
RUN_IDLE	Accept a control start
RUN_VALIDATE	Validate operation, key availability, message length, stride, and batch
RUN_KEY_CLEAR	Pulse core clear_key; continue to read for load or finish for clear
RUN_KEY_AR	Issue one key read address on gmem1
RUN_KEY_R	Capture seed and check RLAST/RRESP
RUN_KEY_LOAD	Hold core load-key valid until accepted
RUN_KEY_WAIT	Wait for hardware SHA, scalar clamp, point multiplication, and compression
RUN_SIGN	Run message reader, core, completion FIFO, and signature writer concurrently
RUN_SUMMARY_AW	Issue summary write address on gmem3
RUN_SUMMARY_W	Transfer the 512-bit summary
RUN_SUMMARY_B	Wait for summary write response
RUN_DONE	Pulse the Vitis done condition and return idle

The message sub-FSM is MSG_IDLE, MSG_AR, MSG_R, and MSG_HOLD. It issues one read only when fewer than 64 core contexts are reserved, captures the beat, and holds it until the core ready/valid handshake. For odd batches it injects one zero-message dummy so the paired compressor cannot strand a final real point.

The signature writer sub-FSM is WR_IDLE, WR_AW, WR_W, and WR_B. A 64-entry 528-bit completion FIFO stores {tag,signature} because the core has no output backpressure. A context remains reserved until its AXI write response arrives, or until an internal dummy result retires.

Summary word

Bits	Field
63:0	payload_cycles from command start through final retirement
127:64	core_window_cycles from first core input through last real core output
191:128	output_span_cycles between first and last real outputs
255:192	key_load_cycles
319:256	message_read_beats
383:320	key_read_beats
447:384	signature_write_beats
479:448	completed signature write responses
480	Core key-loaded flag
481	Internal error, including core error
482	AXI response error
483	Framing/tag/protocol error
484	Invalid command argument
491:485	Completion FIFO high-water mark
498:492	Maximum reserved contexts

fast64_cached_sign_benchmark_engine

Source: bench/rhdl/rtl/fast64_cached_sign_benchmark_engine.sv.

This parameterless on-chip benchmark loads a fixed seed, generates messages, feeds the cached core, and XORs all signatures. It measures core cycles without AXI message/signature traffic.

Ports

Inputs clk, rst, start, and 32-bit batch control a run. Outputs busy, done, sent, received, cycle_count, key_load_cycles, first_output_cycle, output_span, public_key, signature_checksum, and internal_error expose progress and validation data.

deterministic_message

The function accepts 32-bit vector. For each of 64 output bytes it selects one byte of vector according to byte_index mod 4, then adds 3*byte_index modulo 256. Tests reproduce the same mapping in Rust/Dalek.

The engine uses seed bytes 00,01,...,1f in the low-to-high packed order. It records the first cycle at which key_loaded is seen, then continuously offers messages while sent < batch. Every returned signature is XORed into a 512-bit checksum. output_span is last-output cycle minus first-output cycle.

fast64_benchmark_kernel

Source: bench/rhdl/rtl/fast64_benchmark_kernel.sv.

This AXI-Lite-only Vitis wrapper instantiates fast64_cached_sign_benchmark_engine. It has no external-memory master and is for focused throughput/cycle measurement.

Parameters and ports

C_S_AXI_CONTROL_ADDR_WIDTH defaults to 8 and sizes AWADDR/ARADDR. C_S_AXI_CONTROL_DATA_WIDTH defaults to 32 and sizes WDATA, WSTRB, and RDATA. Ports are ap_clk, active-low ap_rst_n, interrupt, and the same AXI-Lite channel signals documented for the I/O kernel.

Its address constants are ADDR_AP_CTRL, ADDR_GIE, ADDR_IER, ADDR_ISR, ADDR_BATCH, ADDR_CYCLES, ADDR_SPAN, ADDR_SENT, ADDR_RECEIVED, ADDR_PUBLIC_CHECKSUM, ADDR_SIGNATURE_CHECKSUM, ADDR_KEY_LOAD_CYCLES, and ADDR_INTERNAL_ERROR. The public-key and signature checksums occupy consecutive 32-bit words beginning at their base addresses.

Legacy fast64_sign_benchmark_engine

Source: bench/rhdl/rtl/fast64_sign_benchmark_engine.sv.

This engine drives fast64_sign_core, not the active cached core.

Parameters

Parameter	Default	Meaning
CONTEXTS	64	Context count passed to the legacy signer
CONTEXT_BITS	6	Context index width passed to the legacy signer
FIXED_KEY	0	When nonzero, every vector uses seed vector zero; otherwise each tag gets a different deterministic seed

Its ports are clk, rst, start, batch, busy, done, sent, received, cycle_count, first_output_cycle, output_span, public_key_checksum, and signature_checksum.

Helper functions

deterministic_seed

Input vector is 32 bits. The function produces 32 bytes; byte i is vector[7:0]*71 + i modulo 256. With FIXED_KEY enabled, the caller supplies zero as vector, so every request receives the same seed.

deterministic_message

Input vector is 32 bits. This function is identical to the cached benchmark function: it cycles through the four vector bytes and adds three times the byte index. Returned public keys and signatures are XORed into their respective checksums.